| Model Title | Date |
|---|---|
| Chip Scale Package (CSP) Solder Joint Reliability and Modeling | Mar 23, 2012 04:27pm |
| Threshold Voltage Shift in 0.1 μm Self-Aligned-Gate GaAs MESFETs Under Bias Stress | Mar 22, 2012 04:12pm |
| Charge Trapping Mechanism under Dynamic Stress and its Effect on Failure Time | Mar 22, 2012 10:50am |
| Polarity-Dependent Device Degradation in SONOS Transistors Due to Gate Conduction | Jan 16, 2012 04:40pm |
| Scintillation Breakdowns and Reliability of Solid Tantalum Capacitors | Jan 16, 2012 02:21pm |
- A quantitative mathematical model.
- Identifies a root cause failure mechanism.
- Identifies the environmental stresses that accelerate the failure mechanism.
- Model's parameters are based on test, field and/or simulated data.
The models and references contained herein have been compiled from the open literature and government and nongovernment technical reports and are intended to be used for reference purposes only. Neither the United States Government, Wyle Laboratories nor Quanterion Solutions Incorporated warrant the applicability and accuracy of these models. The user is further cautioned that the models and references contained herein may not be used in lieu of other contractually cited references and specifications.
Publication of these models and references is not an expression of the opinion of The United States Government or Wyle Laboratories or Quanterion Solutions Incorporated as to the quality of any model mentioned herein and any use for advertising or promotional purposes of these models or references in conjunction with the name of The United States Government, or Wyle Laboratories or Quanterion Solutions Incorporated without written permission is expressly prohibited.

