Compact Modeling of MOSFET Wearout Mechanisms for Circuit-Reliability Simulation - HCI
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Model Parameters
Name Description Parameter Type Value Units View Sub-Model
IsubSubstrate currentSubModel/EquationView
tfHCI lifetimeVariableNot Specified 
AHCIModel prefactorConstant (Testing Req.)Not Specified 
WDevice gate widthConstant (Dimensions Req.)Not Specified 
EaHCIApparent activation energyConstant (Material Prop.)electron volts 
kBoltzmann's constantConstant (Physical)8.62 x 10^5electron volts per degree Kelvin 
nTechnology dependent constantConstant (Testing Req.)Not Specified 

Failure Mechanism

Title Description
Apparent Activation EnergyThe apparent activation energy (Eahci) can be negative or positive depending on the device technology, but typical values are within -0.1 to -0.2 eV.
Hot Carrier InjectionHot Carrier Injection (HCI) is the phenomenon that carriers at MOSFET’s drain end gain sufficient energy to inject into the gate oxide and cause degradation of some device parameters.
Lifetime ModelsMost successful lifetime models characterize HCI effect with peak substrate current for nMOSFETs and peak gate current for pMOSFETs.

Title Description
Channel LengthFor short-channel devices, Vdsat is channel-length (L)-dependent.

Title Description
Technology TypeModels are valid at least down to 0.25μm technology. In the generations beyond (0.25−0.07μm), research has shown that existing lifetime models remain more or less applicable at low voltages.

Title Description
Effective ThicknessEffective thickness of the channel “pinchoff” region are typically within √100 nm to √300 nm.

Uncertainty Limits
Type Uncertainty

Data or Information Needed from Outside Sources
Category Source Description
Scaling FactorUserTechnology-dependent constant (n)
Scaling FactorUserModel prefactor (AHCI)
Scaling FactorUserModel constant (C2)
Rated Electrical Load(s)UserThreshold voltage (Vt)

Bibliographic Citation
Published Status Source Type Title Authors
PublishedArticle/PaperCompact Modeling of MOSFET Wearout Mechanisms for Circuit-Reliability SimulationJin Qin,
Joseph B. Bernstein,
Xiaojun Li
The integration density of state-of-the-art electronic systems is limited by the reliability of the manufactured integrated circuits at a desired circuit density. Design rules, operating voltages, frequencies, and temperatures are precisely chosen to ensure correct product functional operation over its intended lifetime. Thus, in order to obtain the overall performance and functionality bounded by various design and manufacturing constraints, the integrated circuit reliability must be modeled and analyzed at the very beginning of design stages. This paper reviews some of the most important intrinsic wearout mechanisms of MOSFETs (including hot-carrier injection, time-dependent dielectric breakdown, and negative bias temperature instability) and introduces new accelerated-lifetime and SPICE compact models of these wearout mechanisms. Based on these circuit-aging models, a new SPICE reliability simulation approach is proposed and demonstrated with a simplified SRAM design on a commercial 90-nm technology to help designers understand device-failure behaviors, predict circuit reliability, and improve product robustness.
Report # Publication Name Volume # Publisher Name
N/AIEEE Transactions on Device and Materials Reliability8-1N/A
Publication Date Pages Source URL Copyright Info

Technical Point of Contact (PoC)
Xiaojun Li
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Aug 16 at 1:04 pm
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