Semiconductor Device Qualification
Microelectronics integration density is limited by the reliability of the manufactured product at a desired circuit density. Design rules, operating voltage and maximum switching speeds are chosen to insure func tional operation over the intended lifetime of the product. In order to determine the ultimate performance for a given set of design constraints, the reliability must be modeled for its specific operating condition. Thus, Reliability modeling for the purpose of lifetime prediction is the ultimate task of a failure physics evaluation. Unfortunately, all the industrial approaches to reliability evaluation fall short of predicting failure rates or wear-out lifetime of semiconductor products. This is attributed mainly to two reasons; the lack of a unified approach for predicting device failure rates and the fact that all commercial reliability evaluation methods rely on the acceleration of one, dominant, failure mechanism.
Over the past several decades, our knowledge about the root cause and physical behavior of the critical failure mechanisms in microelectronic devices has grown significantly. Confidence in the reliability models have lead to more aggressive design rules that have been successfully applied to the latest VLSI technology. One result of improved reliability modeling has been accelerated performance, beyond the expectation of Moore's Law. A consequence of more aggressive design rules has been a reduction in the weight of a single failure mechanism. Hence in modern devices, there is no single failure mode that is more likely to occur than any other as guaranteed by the integration of modern failure physics and modern simulation tools in the design process. The consequence of more advanced reliability modeling tools is a new phenomenon of device failures resulting from a combination of several competing failure mechanism.
Today, reliability device simulators have become an integral part of the design process. These simulators successfully model the most significant physical failure mechanisms in modern electronic devices, such as Time Dependent Dielectric Breakdown (TDDB), Negative Bias Temperature Instability (NBTI), Electromigration (EM) and Hot Carrier Injection (HCI). These mechanisms are modeled throughout the circuit design process so that the system will operate for a minimum expected useful life. Modern chips are composed of tens or hundreds of millions of transistors. Hence, chip level reliability prediction methods are mostly statistical. Reliability prediction tools, now model the failure probability of chips at the end of life by analyzing only the single dominant wearout mechanism. Modern prediction tools do not predict the random, post burn-in, failure rate that would be seen in the field.
Chip and packaged system reliability is still measured by failure rate in FIT. The FIT is a unit, defined as one failure per billion part hours. The semiconductor industry provides an expected FIT for every product that is sold based on operation within the specified conditions of voltage, frequency, heat dissipation and etc. Hence, a system reliability model is a prediction of the expected mean time between failures (MTBF) for an entire system as
the reciprocal of the sum of the FIT rates for every component. The failure rate of a component can be defined in terms of an acceleration factor, AF, as (Equation 1):
where "Number of failures" and "Number of tested" are the number of actual failures that occurred as a fraction of the total number of units subjected to an accelerated test. The acceleration factor, AF, must be supplied by the manufacturer since only they know the failure mechanisms that are being accelerated in the High Temperature Operating Life (HTOL) and it is generally based on a company proprietary variant of the MIL-HDBK-217 approach for accelerated life testing. The true task of reliability modeling, therefore, is to choose an appropriate value for AF based on the physics of the dominant failure mechanisms that would occur in the field for the device.
The HTOL qualification test is usually performed as the final qualification step of a semiconductor manufacturing process. The test consists of stressing some number of parts, usually about 100, for an extended time, usually 1000 hours, at an accelerated voltage and temperature. Two features shed doubt on the accuracy of this procedure. One feature is lack of sufficient statistical data and the second is that companies generally present zero-failure results for their qualification tests. Parts are stressed at relatively low levels to guarantee zero failures during qualification testing in accordance with their guidelines. Zero failures results in zero real data and the true statistical confidence is mathematically imaginary. The assumption, then, is that no more than one failure occurred during the accelerated test and substitute 1/2 failure to circumvent this imaginary confidence dillema. This results, based on our example parameters, in a reported FIT = 5000/AF, which can be almost any value from less than 1 FIT to more than 500 FIT, depending on the conditions and model used for the voltage and temperature acceleration.
The accepted approach for measuring FIT would, in theory, be reasonably appropriate if there is only a single dominant failure mechanism that is excited equally by either voltage or temperature. For example, EM is known to follow Black's equation (described later) and is accelerated by increased stress current in a wire or by increased temperature of the device. If, however, multiple failure mechanisms are responsible for device failures, each failure mechanism should be modeled as an individual "element" in the system and the component survival is modelled as the survival probability of all the "elements" as a function of time.
If multiple failure mechanisms, instead of a single mechanism, are assumed to be time-independent and independent of each other, FIT (constant failure rate approximation) should be a reasonable approximation for realistic field failures. Under the assumption of multiple failure mechanisms, each will be accelerated differently depending on the physics that is responsible for each mechanism. If, however, an HTOL test is performed at an arbitrary voltage and temperature for acceleration based only on a single failure mechanism, then only that mechanism will be accelerated. In that instance, which is generally true for most devices, the reported FIT (especially one based on zero failures) will be meaningless with respect to other failure mechanisms.
Individual Failure Mechanism Lifetime Model
Relentless scaling for better performance keeps generating new reliability challenges to every aspects of the process technology. EM, the main reliability concern of interconnects, needs to be handled carefully because feature size decreasing and temperature increasing pose dual threats towards new interconnect technology. To meet the performance and reliability requirement, copper interconnects have gradually take the place of Al(Cu) metallization in the past few years, due to its low resistivity and high resistance towards electromigration. Copper interconnects have different EM characteristics compared with aluminum. It is interface dominated  and has larger activation energies .
TDDB has always received much attention because device scaling keeps driving the oxide thickness down but the supply voltage scaling doesn't keep pace. The direct impact of this non-ideal voltage scaling is the increase of gate leakage and tunneling current which decreases the oxide lifetime. An empirical observation is that if gate oxide thickness reduces by ΔT∞
(in nm) by scaling, the leakage current will increase  by:
and TDDB lifetime will reduce by the same factor. Oxide breakdown related failures are often reported in device burn-in test of deep submicron technologies , . Device scaling also increases susceptibility to another failure mechanism: NBTI, which occurs primarily in p-channel MOSFETs with negative gate voltage bias. The interface-trap density generated by NBTI has an inverse proportionality to oxide thickness (T∞
) which means NBTI becomes more severe for ultrathin oxides , while the NBTI generated fixed charge has no thickness dependence. Like NBTI for PMOS, HCI induces interface states and causes degradation of NMOS. Although well contained by channel engineering, it still shows up in real applications .
To model system reliability, all these intrinsic failure mechanisms should be considered since any one of them may cause system failure. Various lifetime models have been proposed for each failure mechanism. As our goal is to show the unique characteristics of system lifetime and voltage and temperature acceleration, we will adapt the generally accepted models.
Failure rate model and acceleration factors for EM, HCI, TDDB and NBTI are listed below.
From the well known Black's equation  and Arrhenius model, the failure rate for EM can be expressed as (Equation 2):
where J is the current density in the interconnect, k is Boltzmann's constant, T is absolute temperature in Kelvin, EaEM is the activation energy, and n is a constant. Both EaEM
and n depend on the interconnect metal. Nowadays copper/low-K dielectric material has been rapidly replacing aluminum alloy/SiO2
-based interconnect. For copper, n has been reported with values between 1 and 2  and EaEM
varies between 0.7eV and 1.1eV . In Eq. (2), current density J can be replaced with a voltage function (Equation 3):
where C, W and H are the capacitance, width and thickness of the interconnect, respectively. f is the frequency, p is the toggling probability. So EM is also a function of voltage (Equation 4):
Based on the empirical HCI voltage lifetime model proposed by Takeda 
and the Arrhenius relationship, HCI failure rate HCI can be modeled as (Equation 5):
is a technology related constant, EaHCI
is the activation energy, varies between -0.1eV ~ -0.2eV . The negative activation energy means HCI becomes worse at low temperature.
The exponential law for TDDB failure rate voltage dependence has been widely used in gate oxide reliability characterization and extrapolation. Combining with the Arrhenius relationship for temperature dependence, TDDB failure rate (Equation 6) is:
is a device related constant and EaTDDB
is the activation energy. EaTDDB
normally falls in the range of 0.6eV ~ 0.9eV .
Like TDDB, NBTI voltage dependence can also be modeled by the exponential law , considering the temperature dependence together, NBTI failure rate is (Equation 7):
is a constant and EaNBTI
is the activation energy which has been reported to vary from 0.1eV to 0.84eV , .
System Voltage and Temperature Acceleration
Assuming there is no interaction among failure mechanisms, a system's failure rate can be obtained by sum-of-failure-rate since all failure mechanisms contribute to system failures (Equation 8):
The system acceleration factor can be expressed as (Equation 9):
Given the models of individual failure mechanisms, the system acceleration factor (Equation 9) can be further expressed as (Equation 10):
are failure percentages of EM, HCI, TDDB and NBTI at stress conditions (VO
), respectively. The advantage of using these failure percentages here is to simplify the derivation process without the need to find out the absolute failure rate for each failure mechanism.
For property issues, original microelectronic device lifetime data is rarely reported in literature. In order to reveal the characteristics of temperature and voltage acceleration at the system level, we do lifetime simulation by using the models given above. The system is assumed to be made with 0.13μm technology and the oxide thickness is 3.2nm. Nominal operating conditions are VO
= 1.3V , TO
= 75°C. HCI, TDDB and NBTI are assumed to contribute equally to system failures at nominal conditions. All the acceleration parameters are extracted from published result related to 0.13m technology (HCI , TDDB  and NBTI ) and listed in Table 1. We assume VO
= 75°C. We assume VO
= 1.3V, TO
Table 1. Simulation Parameters for EM, HCI, TDDB and NBTI
A. Non-Arrhenius Temperature Acceleration
||Voltage Acceleration Parameter
||Activation Energy (eV)
as the activation energy estimated from accelerated tests at (Vi
) and (Vi
,TA). If the Arrhenius relationship still holds at system level,
should be the same for all Ti
. The system temperature acceleration factor
can be calculated as (Equation 11):
are the percentages of EM, HCI, TDDB and NBTI failure at (Vi
), respectively. Using the parameters given in Table I and set TA
=125°C, we did EaSYS
estimation at various Ti
under three voltages: 1.17V, 1.30V and 1.43V and show the results in Fig. 1. The simulation result clearly shows that EaSYS is not a constant. It depends on the stress voltage Vi
and the stress temperature Ti
Figure 1. System activation energies estimated from simulated failure rate at (Vi, Ti) and (Vi, TA). Vi=1.17V, 1.30V and 1.43V. At given Vi, TA=125 °C and Ti varies from 25°C to 124°C. (Click to Zoom)
At given Vi
is an increasing function of Ti
. The reason is that the failure mechanism with the larger activation energy will increase its failure percentage at high temperature at a given stress voltage. For illustration, if |TA
| is considerably small, system activation energy can be approximated by (Equation 12):
From Equation 12, we can find that at any given EaEM
, depends on:
The failure mechanism with the largest activation energy will be accelerated the most as temperature increases and its failure percentage will increase accordingly.
is generally estimated from high temperature acceleration testing, using that activation energy tends to give an optimistic projection at low temperature. For an example, if the acceleration tests were done at (1.43V, 125°C) and (1.43V, 115°C), the estimated EaSYS
is 1.0eV . Using this activation energy to extrapolate system failure rate at (1.43V, 50°C) will result in an optimistic estimation which is 1/14 of the real rate because the "true" EaSYS
is 0.60eV .
B. Stress-Dependent Voltage Acceleration Factor
To show the characteristic of voltage acceleration,
we assume that follows the exponential law (Equation 13):
is the voltage acceleration
is shown below (Equation 14):
have the same meaning as in Eq. (11). Simulation was done with parameters given in Table 1 and the estimated γSYS
is shown in Fig. 2. The result shows that γSYS
varies according to Vi
. For approximation, if the difference between VA
is reasonably small,
can be approximated by Equation 15:
also depends on the failure percentages and the
voltage acceleration parameters. As shown in Fig.2, at 125°C, γaSYS
is larger at higher stress voltage because TDDB together with NBTI dominate here and the higher voltage accelerates them more than EM and HCI.
Figure 2. Estimated SYS from failure rates at accelerated conditions (Vi, Ti) and (VA, Ti). Ti=25°C, 75°C and 125 °C. For each Ti, VA = 1.56V , Vi varies from 1.04V to 1.55V. (Click to Zoom)
estimated at (125°C, 1.55V) to extrapolate system failure rate at low voltage will give an optimistic estimation. At 125°C and Vi
= 1.55V, γSYS
is estimated to be 10.0, while we will get 7.0 if Vi
= 1.30V . There is about 5X difference in failure rate extrapolation.
C. Combined Voltage and Temperature Acceleration Factor
The effect of voltage and temperature acceleration together on system acceleration is further complicated by the interplay between the factors, as shown above. Since there is no universal EaSYS
if multiple failure mechanisms are involved, using AFT
with one activation energy and AFV
with one voltage acceleration parameter for reliability extrapolation is not appropriate. Taking the simulation above as an example, we find out that failure rate estimation using the multiplication model gives an optimistic result. The real system failure rate at (50°C, 1.30V) is 20X that of the estimated failure rate using the multiplication model with EaSYS
from high temperature, high voltage acceleration test at (125°C, 1.55V).
Qualification Based on Failure Mechanism
It is a matter of great complexity to build a system lifetime model to fit all temperatures and voltages if there are multiple failure mechanisms involved. The conventional extrapolation method using one EaSYS
tends to give an optimistic estimation. For reliability qualification considering multiple failure mechanisms, acceleration tests should be designed to accelerate the target failure mechanism with specific stress conditions. This is workable because each failure mechanism has its unique activation energy and voltage acceleration parameter. Among these failure mechanisms, only HCI has negative activation energy while others' are positive. This means lowering stress temperature will accelerate HCI while decelerating the other three failure mechanisms. HCI also has a comparable large γ, so at low temperature and reasonable high voltage, HCI failure will dominate. For EM, since the copper interconnect has a larger activation energy and small γ(< 2), acceleration tests should be designed with high temperature and low voltage. Traditional acceleration tests with high temperature and voltage can be applied to accelerate TDDB and NBTI since both have large voltage acceleration parameter and activation energy. The failure percentage of each failure mechanism at various accelerated conditions is shown in Fig. 3.
Figure 3. Failure percentages of EM, HCI, TDDB and NBTI at different accelerated conditions. (Click to Zoom)
For semiconductor devices, reliability modeling at the system level is complicated by the involvement of multiple failure mechanisms which have the same stress factors-voltage and temperature. The Arrhenius relationship with one activation energy for all temperature is shown to be not valid at the system level if these failure mechanisms don't have the same activation energy. The same happens to the modeling of voltage dependence. Using the exponential law with only one constant coefficient is a good option for an individual failure mechanism, but not for a system. We propose a failure mechanism-based qualification method which quantifies each failure mechanism through acceleration testing with specifically designed stress conditions.
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